Complete the architecture to describe the sequential circuit shown below:

The output two should go high if the input has been high on both of the past two clock cycles, otherwise it will be low.

library IEEE; use IEEE.std_logic_1164.all; entity twohigh is port( clk : in std_logic; input : in std_logic; two : out std_logic ); end twohigh; architecture synth of twohigh is begin -- You got this. end;

Are you confident about this change? (select one to recompile)

Compiler/test output: