VHDLweb
Fill in the architecture to implement a 7-bit thermometer decoder.
The 3-bit input represents the values 0-7, and the result should have the
corresponding number of bits set high on the output. The bits should go on
from "least" to "greatest", like mercury rising in a thermometer.
library IEEE;
use IEEE.std_logic_1164.all;
entity thermometer is
port(
value : in std_logic_vector(2 downto 0);
therm : out std_logic_vector(6 downto 0)
);
end thermometer;
architecture synth of thermometer is
begin
-- This doesn't work for most of the cases...
therm <= "0000000";
end;
Are you confident about this change? (select one to recompile)