Write a testbench to check that the module
adder actually performs correctly as a 4-bit adder.
You probably want to use some kind of test generation, rather than writing out all the cases. A VHDL
for loop might be useful:
for INDEXVAR in MIN to MAX loop -- loop body, which can use INDEXVAR end loop;
Note that INDEXVAR is an integer (not an
std_logic_vector), so you'll need to convert it to the appropriate type if you hope to do any comparisons. Take a look at the reference sheet for how to do conversions.
-- Testbench for 4-bit adder library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; entity adder_test is -- No ports, since this is a testbench end adder_test; architecture test of adder_test is component adder is port( a : in unsigned(3 downto 0); b : in unsigned(3 downto 0); sum : out unsigned(3 downto 0) ); end component; begin end test;
Are you confident about this change? (select one to recompile)