Complete the architecture below to implement this block diagram with submodules thing1 and thing2. (Have no fear, these things are tame.)

You'll need to base your component declarations on these entities:

entity thing1 is
  port(
      s : in std_logic;
      t : in std_logic;
      y : out std_logic_vector(3 downto 0)
  );
end thing1;


entity thing2 is
  port(
      e : in std_logic_vector(3 downto 0);
      f : in std_logic;
      g : out std_logic_vector(3 downto 0)
  );
end thing2;

Starter code

library IEEE; use IEEE.std_logic_1164.all; entity funinabox is port( a : in std_logic; b : in std_logic; result : out std_logic_vector(3 downto 0) ); end funinabox; architecture synth of funinabox is begin end;

Are you confident about this change? (select one to recompile)

Compiler/test output: