VHDLweb
Complete the architecture below to display the value of the 4-bit input S on a 7-segment display. The output should be a vector of bits corresponding to the LED segments, in the order "abcdefg". The display is active low, meaning that to turn an segment on, you should set the corresponding bit to 0.
Note that there is more than one correct way to do this, so ignore the pass/fail result of the test and just examine the output to confirm that it's what you wanted.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sevenseg is
port(
S : in unsigned(3 downto 0);
segments : out std_logic_vector(6 downto 0)
);
end sevenseg;
architecture synth of sevenseg is
begin
segments <= "0000000";
end;
Are you confident about this change? (select one to recompile)