Build an 8-bit one-hot counter (i.e., one bit is high at a time, counting up from the LSB to the MSB and then repeating). When reset, the value should be 0000_0001.

library IEEE; use IEEE.std_logic_1164.all; entity onehot is port( clk : in std_logic; reset : in std_logic; count : out std_logic_vector(7 downto 0) ); end onehot; architecture synth of onehot is begin count <= "00000000"; end;

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Compiler/test output: