VHDL uses '<=' for assignment (where most software languages use '=').

Complete the architecture below to implement a three-input NAND gate: \(Y = \overline{ABC}\)

library IEEE; use IEEE.std_logic_1164.all; entity nand3 is port( a : in std_logic; b : in std_logic; c : in std_logic; y : out std_logic ); end nand3; architecture synth of nand3 is begin -- Your code here end;

Are you confident about this change? (select one to recompile)

Compiler/test output: