A powerful construct for specifying combinational logic is when/else:

OUTPUT <= VALUE when (CONDITION) else OTHER_VALUE;


Complete the architecture below to build a 2:1 multiplexer. The inputs A and B are each 1 bit, and the select line S is a single bit. When S is low, Y should have the value of A; when S is high, it should have the value of B.

library IEEE; use IEEE.std_logic_1164.all; entity mux1bit is port( a : in std_logic; b : in std_logic; s : in std_logic; y : out std_logic ); end mux1bit; architecture synth of mux1bit is begin -- Your code here end;