Build a module which decrements all of the values stored in a 16-word x 8-bit RAM by 1. Your module should not modify memory until the run signal is high; then it should go through each word in the memory and decrement its value. After working through the entire RAM, it should halt until the run signal is asserted again.

The RAM is single-ported, so you you can't read and write simultaneously. You'll need to read the value and write it back on the next clock cycle (or later, if you prefer).

This is a tricky problem so you might start just by reading all of the memory values, or by writing a constant value to each address. Once you've got a handle on reading and writing, you can build the state machine to put it all together.

Note that you don't need to instantiate the RAM; the testbench will do that and connect it to your module.

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity decrementmem is port( clk : in std_logic; run : in std_logic; -- When this is asserted, begin one pass through the memory -- Signals below are connected to the RAM inside the testbench addr : out unsigned(3 downto 0); dataRead : out std_logic_vector(7 downto 0); dataWrite : out std_logic_vector(7 downto 0); writeEnable : out std_logic ); end; architecture synth of decrementmem is constant ADDR_WIDTH : natural := 4; constant RAM_DEPTH : natural := 2**ADDR_WIDTH; begin end;