VHDLweb
Build a 4-bit binary counter which counts from 0 to 9, and then rolls over back to 0. The counter should have a synchronous reset signal which resets the value to 0.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity countto is
port(
clk : in std_logic;
reset : in std_logic;
count : out unsigned(3 downto 0)
);
end countto;
architecture synth of countto is
begin
count <= 4d"0";
end;
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