Build a 3-bit binary counter with a synchronous reset and an enable signal. The counter should increment on each clock cycle when enable is high; otherwise it should remain the same. When reset, the counter should be 000.

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity counter_enable is port( clk : in std_logic; reset : in std_logic; enable : in std_logic; count : out unsigned(2 downto 0) ); end counter_enable; architecture synth of counter_enable is begin end;

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Compiler/test output: