VHDLweb
Write a testbench to check that the module andgate actually performs as an AND gate.
Your code should print the word "failed" if the DUT fails any of your tests. If the testbench does not print the word "failed", the test is assumed to pass.
-- Testbench for AND gate
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
entity and_test is
-- No ports, since this is a testbench
end and_test;
architecture test of and_test is
component andgate is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic
);
end component;
begin
end test;
Are you confident about this change? (select one to recompile)