Fill in the architecture to build a simple ALU. The operands are 4 bits each.
The operation should be performed according to the following table:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity alu is port( a : in unsigned(3 downto 0); b : in unsigned(3 downto 0); s : in std_logic_vector(1 downto 0); y : out unsigned(3 downto 0) ); end alu; architecture synth of alu is begin -- You've got this! end;
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