Write a testbench to check that the module abc computes \(Y = AB + \overline{B}C\)

As before, your code should print the word "failed" if the DUT fails any of your tests. If the testbench does not print the word "failed", the test is assumed to pass.

-- Testbench for AB+!BC library IEEE; use IEEE.std_logic_1164.all; use std.textio.all; entity abc_test is -- No ports, since this is a testbench end abc_test; architecture test of abc_test is component abc is port( a : in std_logic; b : in std_logic; c : in std_logic; y : out std_logic ); end component; begin end test;

Are you confident about this change? (select one to recompile)

Compiler/test output: