VHDLweb
Fill in the architecture to compute \(Y = AB + \overline{B}C\)
library IEEE;
use IEEE.std_logic_1164.all;
entity abc is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic
);
end abc;
architecture synth of abc is
begin
-- Your code here
end;
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