Fill in the architecture to compute \(Y = AB + \overline{B}C\)

library IEEE; use IEEE.std_logic_1164.all; entity abc is port( a : in std_logic; b : in std_logic; c : in std_logic; y : out std_logic ); end abc; architecture synth of abc is begin -- Your code here end;

Are you confident about this change? (select one to recompile)

Compiler/test output: