Build a tone generator which takes a 24.000 MHz clock signal, and produces a 440 Hz (A4) square wave (i.e., low for half the period and then high for half the period). Since the hardware has no concept of time, you'll need to keep track of clock cycles to do the timing.

Note that if the simulation times out, your clock period is way too long.


Starter code

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity tone440 is port( clk : in std_logic; reset : in std_logic; tone : out std_logic ); end tone440; architecture synth of tone440 is begin tone <= '0'; -- A very flat tone end;

Are you confident about this change? (select one to recompile)

Compiler/test output: