Write a testbench to check that the module `mux41` actually performs correctly as a 4:1 multiplexer. (Hint: it doesn't.)

Your code should print the word "failed" if the DUT fails any of your tests. We'll do some automated testing later to ensure that a correct module passes your tests.
-- Testbench for 4:1 multiplexer library IEEE; use IEEE.std_logic_1164.all; use std.textio.all; entity mux41_test is -- No ports, since this is a testbench end mux41_test; architecture test of mux41_test is component mux41 is port( d : in std_logic_vector(3 downto 0); -- Data port s : in std_logic_vector(1 downto 0); -- Select y : out std_logic -- Result ); end component; begin -- Good luck! end test;

Build output: