Write a testbench to check that the module `adder` actually performs correctly as a 4-bit adder.
You probably want to use some kind of test generation, rather than writing out all the cases. A VHDl `for` loop might be useful:
for INDEXVAR in MIN to MAX loop
-- loop body, which can use INDEXVAR
Note that INDEXVAR is an integer (not an unsigned or std_logic_vector), so you'll need to convert it to the appropriate type if you hope to do any comparisons.
-- Testbench for 4-bit adder
entity adder_test is
-- No ports, since this is a testbench
architecture test of adder_test is
component adder is
a : in unsigned(3 downto 0);
b : in unsigned(3 downto 0);
sum : out unsigned(3 downto 0)