A bus is a set of signals which are grouped together conceptually (and often physically). One way to represent a bus is with std_logic_vector, which is somewhat similar to an array in software programming languages. We can declare a 3-bit input bus called `votes` with
  votes : in std_logic_vector(2 downto 0)
With this declaration, you can use `votes(0)` to refer to bit 0 of `votes`, `votes(1)` for bit 1, and `votes(2)` for bit 2. The `(2 downto 0)` part specifies that this is a 3-bit bus where votes(2) is the MSB and votes(0) is the LSB.

Complete the architecture to build a majority encoder: the output `y` is 1 if the majority (i.e., at least two) of the input bits are 1, and 0 otherwise.
library IEEE; use IEEE.std_logic_1164.all; entity majority is port( votes : in std_logic_vector(2 downto 0); y : out std_logic ); end majority; architecture synth of majority is begin y <= '0'; -- A broken clock is right twice a day... end;

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