VHDLweb
The standard way to control the brightness of LEDs is to switch them on and off very quickly and to vary the duty cycle (the percentage of the time that the LED is on). You'll actually get to do this on the UPduino hardware.
Create a module that takes a 24MHz clock and produces a 1 kHz signal with a 25% duty cycle. That is, the total period should be 1 ms, and the output should be high for only 25% of the time.
Like the previous problem, you'll need to keep track of time using the input clock.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ledduty is
port(
clk : in std_logic;
reset : in std_logic;
led : out std_logic
);
end ledduty;
architecture synth of ledduty is
begin
led <= '0'; -- Not the kind of dimming the customer was hoping for
end;
Are you confident about this change? (select one to recompile)