Write a VHDL module which streams the genome through, and asserts (makes high) the `is_c` signal every time the output is a C. The output should be a copy of the input without any delay.

Adenine A00
Thymine T01
Guanine G10
Cytosine C11

library IEEE; use IEEE.std_logic_1164.all; entity gene_findc is port( clk : in std_logic; nuc_in : in std_logic_vector(1 downto 0); -- Input nucleotide nuc_out : out std_logic_vector(1 downto 0); -- Input nucleotide is_c : out std_logic -- Whether the output nucleotide is a cytosine ); end; architecture synth of gene_findc is begin end;

Build output: