Write a VHDL module which streams the genome through, and asserts (makes high) the found_c signal every time the output is a C. The output should be a copy of the input delayed by exactly one clock cycle.
library IEEE;
use IEEE.std_logic_1164.all;
entity gene_findc is
port(
clk : in std_logic;
nuc_in : in std_logic_vector(1 downto 0); -- Input nucleotide
nuc_out : out std_logic_vector(1 downto 0); -- Input nucleotide
foundC : out std_logic -- Whether the output nucleotide is a cytosine
);
end;
architecture synth of gene_findc is
begin
end;
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