Implement a Mealy state machine which detects the code TGG. The output nuc_out should be a copy of the input, with no delay. The tryp output should be high for one clock cycle synchronzied with the second G.
library IEEE;
use IEEE.std_logic_1164.all;
entity gene_find_tryp is
port(
clk : in std_logic;
nuc_in : in std_logic_vector(1 downto 0); -- Input nucleotide
nuc_out : out std_logic_vector(1 downto 0); -- Input nucleotide
tryp : out std_logic -- Whether the output nucleotide is a cytosine
);
end;
architecture synth of gene_find_tryp is
begin
end;
Are you confident about this change? (select one to recompile)
VHDLweb