You can you the `&` operator to concatenate std_logc and std_logic_vector. For example, the following assignment makes a 7-bit result, where the top two bits are '1', the bottom bit is 0, and the remaining 4 are from the vector `value`.
  y <= "11" & value(3 downto 0) & '0';
Complete the architecture below to divide the 8-bit unsigned input by 2, truncating (ignoring) any fraction. The output should also be 8 bits. Do *not* use the VHDL division or shift operators --- instead, think about what happens when you divide a binary number by 2, and figure out how do that by manipulating bits. If it helps, think about what happens when you divide a decimal number by 10.
library IEEE; use IEEE.std_logic_1164.all; entity div2 is port( operand : in std_logic_vector(7 downto 0); result : out std_logic_vector(7 downto 0) ); end div2; architecture synth of div2 is begin result <= x"00"; -- at least this works for 0 and 1... end;

Build output: