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Complete the design to implement the DDDD.
When you run it, you should see the value of the digits 0-63.
To perform the mod operation correctly, you should use
lowBCD <= count mod 4d"10";
Make sure to use an unsigned constant (e.g., 4d"10", rather than the integer constant 10). If you don't, then the behavior depends on the synthesis/simulation tool, and you may get some ugly surprises. Some things work fine here and fail in Radiant, and vice-versa.
As with the original 7-segment display problem, ignore the pass/fail output and verify by inspection that the result is what you want.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dddd is
port(
value : in unsigned(5 downto 0);
tensdigit : out std_logic_vector(6 downto 0);
onesdigit : out std_logic_vector(6 downto 0)
);
end dddd;
architecture sim of dddd is
component sevenseg is
port(
S : in unsigned(3 downto 0);
segments : out std_logic_vector(6 downto 0)
);
end component;
begin
-- Good luck!
end;
Are you confident about this change? (select one to recompile)