VHDLweb
Write a testbench to check that the module andgate actually performs as an AND gate.
Your code should print the word "failed" if the DUT fails any of your tests (i.e., the DUT doesn't perform as an AND gate for one or more sets of inputs). If the testbench does not print the word "failed", the test is assumed to pass (i.e., you're saying the DUT is a fully-functional AND gate).
To check whether you're writing a good testbench, VHDLweb will run your testbench on multiple DUTs, some of which are correct and some of which are broken. To complete this problem successfully, your testbench should identify every time the DUT is broken by printing a failure message.
-- Testbench for AND gate
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
entity and_test is
-- No ports, since this is a testbench
end and_test;
architecture test of and_test is
component andgate is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic
);
end component;
begin
end test;
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