Just as it's helpful to define intermediate variables in a software program, it is often useful to define intermediate signals to represent part of a hardware computation.

Declaring a signal is just like declaring an input or output port, except that it happens at the top of the architecture, and begins with the keyword `signal`.
architecture synth of adderlogic is
  signal onebit : std_logic;
  signal mybus : std_logic_vector(2 downto 0);
begin
  -- regular architecture
end;
Implement a 3-bit adder without using the addition operator, by writing boolean assignments for each bit. A and B are 3-bit inputs; the result should be a 4-bit output (so there should be no overflow.) This is identical to ES 4 lab 2.

Use intermediate signals for the carry bits.
library IEEE; use IEEE.std_logic_1164.all; entity adderlogic is port( a : in std_logic_vector(2 downto 0); b : in std_logic_vector(2 downto 0); sum : out std_logic_vector(3 downto 0) ); end adderlogic; architecture synth of adderlogic is begin sum <= "0000"; end;

Build output: