You may have noticed that you can't do math on std_logic_vector. That's because `std_logic_vector`s are just collections of bits; they don't have any math operations defined. To enlist VHDL's help to do math with bits, we need the `unsigned` type.
Complete the architecture below to add 1 to the 8-bit input. It should overflow to 0 after it reaches the maximum value.
entity add1 is
operand : in unsigned(7 downto 0);
result : out unsigned(7 downto 0)
architecture synth of add1 is
result <= to_unsigned(1, 8); -- 8-bit constant with the value 1