Write a testbench to check that the module abc computes Y = AB + (!B)C

-- Testbench for AB+!BC library IEEE; use IEEE.std_logic_1164.all; use std.textio.all; entity abc_test is -- No ports, since this is a testbench end abc_test; architecture test of abc_test is component abc is port( a : in std_logic; b : in std_logic; c : in std_logic; y : out std_logic ); end component; begin end test;

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